As disclosed in PTL 1, there is a technology for an information processing apparatus including an external device controller, in which when an external device is connected to the information processing apparatus so as to be capable of communicating therewith, an operation clock is supplied from the external device controller of the information processing apparatus to the external device. Here, generally, the external device is set so as to output data in synchronization with the clock supplied from the external device controller, and the external device controller is configured to latch therein the data output from the external device.
With the use of the above method, the external device controller temporarily stops supply of clocks (corresponding to clock gating) to the external device, thus allowing the supply of data from the external device to the external device controller to be temporarily stopped. For example, when data is accumulated up to the allowed capacity of a reception buffer in the external device controller, the external device controller can stop supply of clocks to stop supply of data, thus preventing an overflow of the buffer as desired even if the capacity of the buffer is small.
Here, if data received by the external device controller from the external device is delayed by one cycle or more with respect to an output clock of the external device controller, it may be difficult to detect the presence or absence of the delay with a configuration as disclosed in PTL 1.